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3. STM32 WB55 Microcontroller Power Architecture

3.1 Power Domain Specifications​

The STM32 WB55CEU microcontroller is designed with a sophisticated partitioned power architecture aimed at enhancing noise isolation and optimizing energy efficiency. This architecture delineates distinct power domains, each serving specific functional blocks within the microcontroller, thereby minimizing cross-interference and ensuring stable operation across various operational states. The power domains are specified as follows:

  • VDD (3.3V Digital):

    The VDD domain is the primary power supply for the microcontroller's core digital logic, General-Purpose Input/Output (GPIO) pins, and digital peripherals, including Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I²C), and Universal Asynchronous Receiver/Transmitter (UART). The current consumption for this domain is specified at 50 mA during active operation at 64 MHz, and it reduces to 1 µA in shutdown mode. To ensure robust power delivery and mitigate high-frequency noise, each VDD pin is equipped with a 100 nF X7R Multilayer Ceramic Capacitor (MLCC) in an 0402 package rated for 10V. These capacitors are strategically placed within a 2 mm proximity to the Integrated Circuit (IC) to maintain low inductance and effective decoupling.

  • VDD_USB (3.3V):

    Dedicated to powering the USB 2.0 Physical Layer (PHY), the VDD_USB domain ensures that USB operations remain electrically isolated from the core digital circuitry. Isolation is achieved through the incorporation of a ferrite bead with a resistance of 600 Ω at 100 MHz between the VDD and VDD_USB supplies. This ferrite bead functions as a high-frequency noise filter, preventing digital switching noise from propagating into the USB circuitry, thereby maintaining signal integrity and compliance with USB standards.

  • VDDA (3.3V Analog):

    The VDDA domain supplies power to analog components, including the Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), and the internal voltage reference. To preserve the fidelity of analog signals and minimize noise coupling, the VDDA supply is subjected to a π-filter configuration comprising a 10 Ω resistor and a combination of 100 nF and 1 µF capacitors at the input. This filtering arrangement effectively attenuates high-frequency noise and stabilizes the analog supply voltage, ensuring precise analog signal processing.

  • VDD_RF (3.3V RF):

    Powering the 2.4 GHz RF transceiver, the VDD_RF domain is isolated from other digital domains to prevent RF noise from disrupting digital operations. The layout incorporates a guard ring with a spacing of 0.3 mm around the RF supply traces, effectively isolating them from adjacent digital nets. This isolation strategy reduces electromagnetic interference (EMI) and preserves the integrity of RF signals, which is critical for reliable Bluetooth Low Energy (BLE) communication.

  • VBAT (1.65–3.6V):

    The VBAT domain serves as a backup power supply for the Real-Time Clock (RTC) and SRAM retention, ensuring data persistence and accurate timekeeping during power outages or low-power states. A Schottky diode (BAT60A) is employed for diode isolation between VBAT and VDD, facilitating efficient power transfer while preventing reverse current flow. This isolation is crucial for maintaining the autonomy of the backup domain without introducing significant voltage drops or power losses.

3.2 Decoupling Network Implementation​

Effective decoupling is essential for maintaining power integrity and minimizing noise within the microcontroller's power domains. The decoupling strategy is bifurcated into local and bulk decoupling networks to address different frequency ranges and noise sources.

  • Local Decoupling:

    Local decoupling involves the placement of 100 nF MLCCs with C0G dielectric properties directly at each VDD pin, as illustrated in Figure 1(a). These capacitors are selected for their low Equivalent Series Inductance (ESL), which is critical for high-frequency decoupling. Utilizing via-in-pad techniques for capacitors in sizes 0402 or smaller further reduces inductance, enhancing the capacitors' effectiveness in filtering high-frequency noise. This proximity ensures that transient voltage spikes and high-frequency noise are swiftly mitigated, maintaining stable supply voltages for sensitive digital circuits.

  • Bulk Decoupling:

    The bulk decoupling network employs 4.7 µF X5R MLCCs in an 0805 package, rated at 6.3V with an ESL below 0.5 nH. These capacitors are positioned at the output of the Switched-Mode Power Supply (SMPS) to stabilize the overall supply voltage and provide energy storage for transient loads. The low Equivalent Series Resistance (ESR) of these capacitors ensures loop stability, preventing oscillations and maintaining efficient power regulation under varying load conditions.

3.3 Grounding Strategy​

A robust grounding strategy is pivotal for minimizing ground noise and ensuring reliable signal transmission across the Printed Circuit Board (PCB). The grounding approach for the STM32 WB55CEU microcontroller encompasses the following elements:

  • VSS Connections:

    All 14 VSS (ground) pins of the microcontroller are connected to a contiguous ground plane fabricated with 2 oz. copper to provide low-impedance paths for return currents. This continuous ground plane minimizes ground potential differences and reduces inductive and resistive losses. The thermal pad associated with the microcontroller is connected to the ground plane via a 4×4 via array, each with a diameter of 0.3 mm, ensuring effective thermal dissipation and robust electrical connectivity to the bottom-layer ground.

  • Partitioning:

    The grounding architecture segregates analog and digital grounds into separate domains—Analog Ground (AGND) and Digital Ground (DGND), respectively. These domains are interconnected at a single-point star ground to prevent digital switching noise from contaminating the analog ground. Additionally, the RF ground is isolated using a 1 nH Murata inductor (LQW15AN1N0C00D), effectively decoupling RF return currents from the digital and analog grounds. This isolation is critical for maintaining signal integrity in RF operations and preventing EMI from affecting other functional blocks.

3.4 Switch-Mode Power Supply (SMPS) Circuit​

The Switch-Mode Power Supply (SMPS) circuit within the STM32 WB55CEU microcontroller is integral to efficient power management, enabling dynamic voltage regulation and reducing power consumption through high-frequency switching. The SMPS implementation adheres to STM32 hardware design guidelines (AN5165) to ensure optimal performance and compliance with electromagnetic compatibility (EMC) standards.

3.4.1 Topology​

The SMPS employs a buck converter topology, as depicted in Figure 1(b). This configuration steps down the input voltage to a lower output voltage, providing the necessary VCORE for the microcontroller's operation.

  • Input:

    The input to the buck converter is the 3.3V supply (VDD_SMPS), which is regulated to maintain a stable input voltage despite fluctuations in the main supply.

  • Output:

    The buck converter outputs a regulated 1.2V (VCORE) through an adjustable feedback loop (VFB_SMPS), ensuring precise voltage levels for the microcontroller's core operations.

  • Switching Frequency:

    The switching frequency is set at 4 MHz, configurable via the RCC_CFGR register. This high frequency allows for the use of smaller passive components, reducing PCB space and improving transient response.

3.4.2 Passive Component Selection​

The selection of passive components is critical for the SMPS's efficiency and stability.

  • Inductors:

    • L1: A 10 nH inductor (Murata LQP15MN10N02D) in an 0402 package is utilized for high-frequency filtering, attenuating switching noise and smoothing the output voltage.

    • L2: A 10 µH inductor (TDK VLS201610ET-100M) in an 0805 package serves as the energy storage element, maintaining continuous current flow during switching cycles.

    • Self-Resonant Frequency (SRF):

      Both inductors are selected to have an SRF exceeding 50 MHz, preventing parasitic resonance and ensuring stable operation at the 4 MHz switching frequency.

  • Capacitors:

    • C_SMPS: A 4.7 µF X7R MLCC in an 0805 package with an ESL below 0.5 nH is employed at the SMPS output to stabilize the regulated voltage and filter out residual switching noise.

    • Placement:

      These capacitors are positioned within 5 mm of the SMPS pins (PF0, PF1) to minimize inductive loops and enhance filtering effectiveness.

3.4.3 Layout Guidelines (AN5165 Compliance)​

Adherence to layout guidelines ensures that the SMPS operates within desired parameters and complies with EMC standards.

  • Critical Paths:

    The Switch (SW) node, encompassing the connection from PF1 through L2 to C_SMPS, is maintained at a length of 10 mm or less. This constraint minimizes inductive and capacitive parasitics, reducing voltage overshoot and ringing, which are detrimental to SMPS stability.

    Parallel routing with RF or clock signals is strictly avoided to prevent coupling of switching noise into sensitive signal paths, thereby maintaining signal integrity across the PCB.

  • Thermal Relief:

    Inductor pads are connected to the ground plane via 0.5 mm thermal spokes. This design mitigates soldering stress by providing controlled thermal pathways, preventing thermal gradients that could lead to mechanical stress or solder joint failures.

3.5 Validation Metrics​

Validation of the power architecture is essential to ensure compliance with performance standards and design specifications. The following metrics are critical for assessing the efficacy of the power domains and SMPS circuit:

  • Power Integrity:

    • VDD Ripple:

      The ripple on the VDD supply must not exceed 30 mV peak-to-peak (mVpp) within a 20 MHz bandwidth under a 100 mA load. This criterion ensures stable voltage delivery to the digital core, minimizing the risk of operational instability or data corruption due to voltage fluctuations.

    • VDDA Noise:

      The noise on the VDDA supply is limited to 10 µV root mean square (µVrms) across the frequency range of 10 Hz to 1 MHz. Low noise levels are imperative for maintaining the accuracy and precision of analog components such as ADCs and DACs.

  • SMPS Efficiency:

    • The SMPS must achieve an efficiency of ≥ 88% at a 10 mA load and ≥ 92% at a 50 mA load. High efficiency reduces power loss and thermal dissipation, enhancing the overall energy efficiency of the system and prolonging battery life in portable applications.

  • Ground Impedance:

    • The ground impedance between VSS pins, measured using a 4-point probe at 1 kHz, must be less than 5 mΩ. Low ground impedance ensures minimal voltage drops and stable reference potentials across the microcontroller, which is essential for reliable operation of high-speed digital and RF circuits.

Figure 1​

  • Figure 1(a): Depicts the decoupling network for VDD pins, illustrating the placement of 100 nF MLCCs in close proximity to each VDD pin to facilitate effective high-frequency noise suppression.

  • Figure 1(b): Illustrates the SMPS schematic, highlighting the arrangement of inductors (L1, L2) and the output capacitor (C_SMPS). This schematic provides a detailed view of the buck converter topology, showcasing the critical components and their interconnections essential for stable voltage regulation.

Conclusion​

The power architecture of the STM32 WB55CEU microcontroller is meticulously engineered to ensure optimal performance, energy efficiency, and noise isolation across its various functional domains. By adhering to the STM32 hardware design guidelines (AN5165) and implementing robust decoupling, grounding, and power regulation strategies, the design effectively minimizes radiated emissions (CISPR 32 Class B) while maintaining signal integrity for BLE operations. The established validation metrics further guarantee that the power architecture meets stringent performance standards, ensuring reliable and efficient operation in advanced embedded applications.